Recent developments in integrated circuit (“IC”) technology have shown remarkable promise in reducing the size of logic and memory circuits from microscale dimensions to nanoscale dimensions. Nanoscale electrical circuits, also called “nanoelectronic tiles,” can be electronically interconnected to configure larger circuit elements called “mosaics.” As a result, it may be assumed that IC component density can be significantly increased by employing mosaics of nanoelectronic tiles, because nanoelectronic tiles occupy less surface area than microscale equivalent IC components. However, nanoelectronic tiles are subject to many of the same limitations associated with microscale circuits. For example, nanoelectronic tiles are subject to Rent's Rule that relates the number of electrical interconnections or pins, Np, to the number of logic gates, Ng, as follows:Np=κNgγ                where proportionality constant, κ, and exponent γ are constants that depend on architecture and implementation of the logic circuit.In most microprocessor architectures, κ typically ranges between 1 and 2, and γ typically ranges between 0.5 and 0.6. According to Rent's rule, as the number of logic gates in an IC increases, the number of electrical interconnections also increases.        
In addition, on chip electrical interconnections interconnecting nanoelectronic tiles, such as a multiplexer/demultiplexer (“MUX/DEMUX”), are approaching the fundamental physical limits of the information-carrying capacity of metal signal lines. For example, FIG. 1 illustrates an exemplary processor/memory interconnection architecture comprised of nanoelectronic tile components. In FIG. 1, central processing unit (“CPU”) 110 retrieves data stored in a particular location in random access memory (“RAM”) 130-132 by providing a logical address, that identifies the particular location in RAM 130-132, to multiplexer/demultiplexer (“MUX/DEMUX”) 120 interconnecting CPU 110 to RAM 130-132. Hierarchically organized MUX/DEMUX stages may be employed to handle the large number of memory addresses located in RAM 130-132. As IC components, such as CPU 110 and RAM 130-132, and electronic interconnections, such as MUX/DEMUX 120, shrink from microscale dimensions to nanoscale dimensions, intrinsic capacitance of the electronic interconnections greatly increases and exceeds that of the nanoscale circuits. As a result, the relative amount of time needed to traverse the multiplexed circuit paths become too long to take full advantage of the high-speed performance offered by nanoscale components. Furthermore, the information carrying capacity of nanoscale electrical interconnections carrying data, power and clock signals is lower that microscale equivalents, and closely spaced signal lines cannot pass high speed signals without creating interference between adjacent signal lines, such as inducing currents in adjacent signal lines. Thus, even though the circuit density can be increased by decreasing the size of IC components, the number of transistors that can be reached in one clock cycle of a clock signal may shrink from 20×106 to less than 2×106.
Nanoscale implementations of computer components, therefore, may fail to take full advantage of the miniaturization offered by mosaics of nanoelectronic tiles, because of limitations in the degree to which the sizes of the interconnections can be decreased constrain the overall size decreases that can be achieved by using nanoscale components. The intrinsic capacitance of the interconnections can greatly exceed that of nanoelectronic tiles within a CPU or mosaics within RAM leading to an interconnection constraint on increasing signal speed. Manufacturers, designers, and users of nanoscale computing devices have recognized a need for an interconnection architecture that provides high-speed interconnections for distributing data, power, and clock signals without the size and signal-speed constraints inherent in currently employed, hierarchically interconnection stages.